Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design

© 1996 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Difference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design methodology or semi-custom design style is proposed Experimental results for each strategy are discussed. Finally, different types of partitioning strategies are showed, taken into account the parallelism of the gates.Peer ReviewedPostprint (published version

Generador de seqüències de test per circuits integrats NMOS

El generador de secuencias de ensayo que se presenta en este artículo utiliza una descripción del circuito a nivel de transistor que representa las redes de transistores de enriquecimiento de las funciones lógicas NMOS mediante grafos no orientados. Para la generación de vectores de ensayo se emplea el algoritmo D, habiendo desarrollado un método enumerativo de búsqueda de caminos en la parte superior del grafo, a partir del camino mínimo que pasa por el flanco que representa el transistor afectado por el fallo

The provision of guidelines for the installation of wind turbines near aeronautical radio stations

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